Flash memory device includes charges, wherein charges are stored in an isolated conductor, commonly referred to as a floating gate, in an FET (field-effect transistor) device. A memory cell (cell transistor) operates by storing electric charge (representing either a binary “0” or “1” state of one data bit) on the floating gate, which is incorporated into a MOS (Metal-Oxide Semiconductor) field-effect transistor. The stored charges affect the VT (threshold voltage) of the transistor, thereby providing a way to read the current through the storage device.
A memory cell typically consists of a transistor, a floating gate, and a control gate above the floating gate in a stacked gate structure. The floating gate, typically composed of polycrystalline silicon (i.e., “polysilicon”), is electrically isolated from the underlying semiconductor substrate by a thin dielectric layer, which is typically formed of an insulating oxide, and more particularly, silicon oxide. This dielectric layer is often referred to as a tunnel oxide layer. The control gate is positioned above the floating gate, and is electrically isolated from the floating gate by a storage dielectric layer. Thus, the floating gate serves as a charge trap region, wherein charges are stored in the charge trap region. Other charge storage devices are constructed to store charges in insulator bulk traps in the FET device, such as MNOS (metal-nitride-oxide-semiconductor), MAOS (metal-alumina-oxide-semiconductor), MAS (metal-alumina-semiconductor), and SONOS (silicon-oxide-nitride-oxide-semiconductor) memory cells.
A programmed memory cell has its VT increased by increasing the amount of negative charge stored on the floating gate, i.e., for given source and drain voltages, the control gate voltage which allows a current to flow between the source and the drain of a programmed memory cell is higher than that of a non-programmed memory cell. Therefore, the state of a memory cell is read by applying a control gate voltage below a predetermined level corresponding to the programmed state, but sufficiently high to allow a current between the source and the drain in a non-programmed memory cell. If a current is detected, then the memory cell is read to be not programmed.
The floating gate memory, such as flash memory, can configure very high density memory. Then, the flash memory is applied to cell phone, music player, movie player, the memory of the image in the digital camera, substitution of the hard disk drive, and so on.
The conventional flash memory is realized by using sense amp in order to measure the current of the floating gate transistor. In FIG. 1A, one of prior arts for the sense amp is illustrated, as published, “A 3.3V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme”, IEEE Journal of Solid-State Circuits, Vol. 30, No. 11, pp 1149-1156, November 1996, and U.S. Pat. No. 6,480,419 and U.S. Pat. No. 5,790,458. Before read, pre-charge transistor 121 is turned on to set a sensing node 120 to high, and another pre-charge transistor 138 resets a latch circuit 130 including a clocked inverter 132 and an inverter 134. In order to read, pre-charge signal PRE is de-activated to high, enable signal PBENB is also de-activated to high, and latch signal LATCH is low, while select signal SLT is activated to high. Then, page selection transistors 122e and 122o connect either an even bit line BLe or an odd bit line BLo to the sensing node 120 for an access. The selected memory cell (not shown) discharges latch node 131 through transfer transistor 126, when low threshold data is stored in the selected memory cell. Otherwise the memory cell does not discharge the latch node 131, thus the latch keeps high. After then, the latched data is transferred to DATA LINE by Y access transistor 140.
In FIG. 1B, another circuit shows the structure of the essential portion of a NAND flash memory device, as a prior art which is published as “A Negative Vth Cell Architecture for Highly Scalable, Excellently Noise-Immune, and Highly Reliable NAND Memories”, IEEE Journal of Solid-State Circuits, Vol. 34, No. 5, pp 675-684, November 1999, and U.S. Pat. No. 6,049,494. Namely a sensing circuit that is concerned with data writing and reading. For the sake of diagrammatic simplification, FIG. 1B shows each unit consisting of a plurality of NAND memory cells whose drains are commonly connected to a bit line. More specifically, each unit comprises a flip-flop circuit 151 and 152 for temporarily holding a data, a bit line BL, NAND memory cells M1 and M32, N-channel transistor Q1 for pre-charging the bit line BL to a predetermined potential, N channel transistor Q2 for connecting the bit line BL to the flip-flop circuit, and N-channel transistor Q3 having both ends connected between a node of the flip-flop circuit on the opposite side to the bit line BL and a bit line side end of the transistor Q2. This transistor Q3 is provided to hold read data and then output a potential corresponding to inverted data of the read data to the bit line BL. The individual terminals of the flip-flop circuit are connected to an I/O line and a BI/O line via a column gate 154 and 155, respectively. The control signals phi.1, phi.2 and phi.3 are generated by sequential control circuit (not shown) for driving operation modes. A phi.1 signal line is connected to the gate of the transistor Q1 to control the pre-charging. A phi.2 signal line and a phi.3 signal line are respectively connected to the gate of the transistor Q2 and the gate of the transistor Q3, and are controlled at predetermined timings. The source of the transistor Q1 is connected to a power supply which provides a high supply voltage (for example, 9V) in write mode and a low supply voltage (for example, 5V) otherwise. The power supply for the flip-flop circuit 151 and 152 is provided as the same manner.
A description will now be given of the operation of copying data of a memory cell (for example, M1). It is assumed that the copying destination cell (for example, M1) has been erased previously, i.e., it has been set ON previously. First, data of the cell (for example, M1) is read out. At this time, the individual transistors of the flip-flop circuit (151 and 152) which receive clocks (not shown) are cut off and are disabled. The transistor Q2 connected to the bit line BL is set off and the transistor Q3 is also set off. Suppose that the bit line BL is pre-charged to a high level and the transistor Q2 is turned on to set the bit line BL in a free running state. After a proper time elapses, the flip-flop circuit (151 and 152) is enabled. When the potential of the bit line BL then is higher than the threshold value voltage of the flip-flop circuit, i.e., when data is written in the cell M1 and the threshold value is high, a node 153 between the bit line BL and the flip-flop circuit is set to a high level. If the cell M1 is left erased, the bit line BL is discharged so that the node 153 is set to a low level. This completes the reading operation. That is, the read data in the cell M1 is latched in the flip-flop circuit.
The conventional flash memory has progressed its miniaturization and as a result there arises difficulties in obtaining necessary current to measure the stored data in the memory cell. The turn-on current of the memory cell should drive the selected bit line because the bit line is relatively heavy and long to connect multiple memory cells. And as shown in the prior arts, the latch circuit including two clocked inverters and switches is controlled by timing generator circuit (not shown) wherein the timing is generated by delay circuits typically. This means that the memory cell should discharge the heavy bit line within the predetermined time. And the ratio between the turn-on current and the turn-off current should be relatively high to differentiate low threshold data and high threshold data, such as several 1000 times different. When the ratio is very low, the leakage current (turn-off current) may also discharge the bit line, which may cause the sensing error because the latch node is discharged whether the threshold voltage of the memory cell is low or high. And also the timing generation for controlling the latch is more difficult because there is no precise timing generator based on the turn-on current.
Furthermore, one of major problem is that the turn-on current through the floating gate MOS transistor is low, around 1 uA or less for the conventional flash memory, as published, “A 90-nm CMOS 1.8-V 2-Gb NAND Flash Memory for Mass Storage Applications”, IEEE Journal of Solid-State Circuits. Vol. 38, No. 11, November, 2003. Even worse in the other types of floating gate memory, such as the nanocrystal memory, the drain current of the memory cell is around 1 nA or less, as published, “Metal Nanocrystal Memories—Part II: Electrical Characteristics”, IEEE Transactions on Electron Devices, Vol. 49, No. 9, September, 2002. And for the single electron memory (SEM) including quantum dot, the drain current is 1.5 p˜3 pA as published, “Room temperature Coulomb oscillation and memory effect for single electron memory made by pulse-mode AFM nano-oxidation process”, 0-7803-4774-9/98 16.6.2 IEDM 1998.
In this respect, there is still a need to improve the floating gate memory, in order to read the memory cell more effectively, even though the memory cell can flow relatively low current. In the present invention, multi-divided bit line architecture is introduced to reduce the parasitic capacitance of the bit line, and reduced swing sense amplifiers are used for reading the memory cell through the multi-divided local bit line. In particular, two-stage sensing scheme is realized for minimizing area penalty, and which improves read access time.
And, the memory cell can be formed from single crystal silicon on the surface of a wafer. Alternatively, the memory cell can be formed from thin film polysilicon layer, because the lightly loaded bit line can be quickly discharged by the memory cell even though the thin film memory cell can flow relatively low current. In doing so, multi-stacked NAND flash memory is realized with the thin film memory cell, which can increase the density of the flash memory within the conventional CMOS process with additional process steps.